Field of the Invention
The present invention relates to an eddy current sensor suitable for detecting a metal film (or conductive film) formed on a surface of a substrate such as a semiconductor wafer. Further, the present invention relates to a polishing method and apparatus for polishing the substrate while monitoring the metal film (or conductive film) formed on the substrate by the eddy current sensor to remove the metal film (or conductive film).
Description of the Related Art
In recent years, high integration and high density in semiconductor device demands smaller and smaller wiring patterns or interconnections and also more and more interconnection layers. Multilayer interconnections in smaller circuits result in greater steps which reflect surface irregularities on lower interconnection layers. An increase in the number of interconnection layers makes film coating performance (step coverage) poor over stepped configurations of thin films. Therefore, better multilayer interconnections need to have the improved step coverage and proper surface planarization. Further, since the depth of focus of a photolithographic optical system is smaller with miniaturization of a photolithographic process, a surface of the semiconductor device needs to be planarized such that irregular steps on the surface of the semiconductor device will fall within the depth of focus.
Thus, in a manufacturing process of a semiconductor device, it increasingly becomes important to planarize a surface of the semiconductor device. One of the most important planarizing technologies is chemical mechanical polishing (CMP). In the chemical mechanical polishing, while a polishing liquid containing abrasive particles such as silica (SiO2) therein is supplied onto a polishing surface such as a polishing pad, a substrate such as a semiconductor wafer is brought into sliding contact with the polishing surface and polished using the polishing apparatus.
In forming the above mentioned multilayer interconnections, there has been performed a process in which grooves for interconnections having a predetermined pattern are formed in an insulating layer (dielectric material) on a substrate, the substrate is then dipped in a plating solution to plate the substrate with copper (Cu), for example, by an electroless plating or an electrolytic plating, and then unnecessary portions of a copper layer is selectively removed from the substrate by a CMP process, while leaving only the copper layer in the grooves for interconnections. In this case, if the substrate is insufficiently polished to leave the copper layer on the insulating layer (oxide film), then the circuits would not be separated from each other, but short-circuited. Conversely, if the copper layer in the interconnection grooves is excessively polished away together with the insulating layer, then the resistance of the circuits on the substrate would be so increased that the entirety of the semiconductor substrate might possibly need to be discarded, resulting in a large loss. This holds true for the cases in which other metal films such as aluminum layer are formed, and then polished by the CMP process.
The polishing apparatus which performs the above-mentioned CMP process includes a polishing table having a polishing surface formed by a polishing pad, and a substrate holding device, which is referred to as a top ring or a polishing head, for holding a semiconductor wafer (substrate). When a semiconductor wafer is polished with such a polishing apparatus, the semiconductor wafer is held and pressed against the polishing surface under a predetermined pressure by the substrate holding device so that the metal film on the semiconductor wafer is removed.
After a polishing process is completed, if a subsequent process is carried out in such a state that the metal film is left on the semiconductor wafer, then problems of short circuit or the like occur, and thus the semiconductor wafer cannot be used. Therefore, after the polishing process is completed, the wafer is separated and moved away from the polishing pad (polishing surface), and then an inspection on the presence of the remaining metal film is carried out. In this manner, although it is possible to confirm the remaining film, it takes time for inspection to reduce wafer processing capability. After the inspection, if the remaining film is detected on the wafer, then it is necessary to carry out repolishing. However, in the case where polishing is carried out after the wafer is moved away from the polishing pad, processing time per wafer increases. That is, the throughput is lowered.
In order to solve the above problem of lowering of the throughput caused by the inspection on the presence of the remaining metal film and the repolishing after the inspection, in Japanese laid-open patent publication No. 2011-23579, there has been proposed a polishing method and apparatus which can shorten inspection time by performing an inspection on whether or not there is a remaining film of a metal film (or conductive film) on a substrate such as a semiconductor wafer during polishing, and can shorten processing time by performing additional polishing of the substrate as it is in the case where the remaining film is detected.